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| MOSEL VITELIC V53C316405A 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C316405A Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 50 50 ns 25 ns 20 ns 84 ns 60 60 ns 30 ns 25 ns 104 ns Features s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh and Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II s Single +3.3V 0.3V Power Supply s TTL Interface Description The V53C316405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory. The V53C316405A offers Page mode operation with Extended Data Output. The V53C316405A has asymmetric address, 12-bit row and 10-bit column. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 1024 x 4 bits, within a page, with cycle times as short as 20ns. These features make the V53C316405A ideally suited for a wide variety of high performance computer systems and peripheral applications. Device Usage Chart Operating Temperature Range 0C to 70C Package Outline K * Access Time (ns) 50 * Power Std. * T * 60 * Temperature Mark Blank V53C316405A Rev. 1.2 March 1998 1 MOSEL VITELIC 24/26-Pin Plastic SOJ/TSOP-II PIN CONFIGURATION Top View VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 311640500-02 V53C316405A VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS Pin Names A0-A11 RAS CAS WE OE I/O1-I/O4 VCC VSS NC Row, Column Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +3.3V Supply 0V Supply No Connect V53C316405A Rev. 1.2 March 1998 2 MOSEL VITELIC Absolute Maximum Ratings* Operating temperature range ..................0 to 70 C Storage temperature range ............... -55 to 150 C Input/output voltage .... -0.5 to min (VCC+0.5, 4.6) V Power supply voltage .......................... -1.0 to 4.6 V Power dissipation .......................................... 0.5 W Data out current (short circuit) ...................... 50 mA *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. V53C316405A TA = 25C, VCC = 3.3 V 0.3V, VSS = 0 V Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. -- -- -- Max. 5 7 7 Unit pF pF pF Capacitance* *Note: Capacitance is sampled and not 100% tested. Block Diagram 4096 x 4 I/O1 I/O2 I/O3 I/O4 Data In Buffer WE CAS 4 Data Out Buffer 4 OE No. 2 Clock Generator 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Column Address Buffers (10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (12) 12 12 Row Address Buffers (11) 12 Row Decoder 4096 Memory Array 4096 x 1024 x 4 1024 x4 4 RAS No. 1 Clock Generator Voltage Down Generator VCC 311640502-04 VCC (internal) V53C316405A Rev. 1.2 March 1998 3 MOSEL VITELIC DC and Operating Characteristics (1-2) TA = 0C to 70C, VCC = 3.3 V 0.3V, VSS = 0 V, VT = 2ns unless otherwise specified. Symbol ILI ILO V53C316405A Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Access Time V53C316405A Min. -10 Typ. Max. 10 Unit A A Test Conditions VSS VIN VCC+0.3V VSS VOUT VCC+0.3V RAS, CAS at VIH tRC = tRC (min.) Notes 1 -10 10 1 ICC1 VCC Supply Current, Operating VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh VCC Supply Current, EDO Page Mode Operation VCC Supply Current, during CAS-before-RAS Refresh VCC Supply Current, CMOS Standby 50 60 50 40 2 mA 2, 3, 4 ICC2 ICC3 mA RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2, 4 50 60 50 60 50 60 50 40 35 30 50 40 1.0 mA ICC4 mA Minimum Cycle 2, 3, 4 ICC5 mA 2, 4 ICC6 mA RAS VCC - 0.2 V, CAS VCC - 0.2 V, other input pins VSS 1 VCC VIL VIH VOL VOH VOL VOH Power Supply Voltage Input Low Voltage Input High Voltage TTL Output Low Voltage TTL Output High Voltage CMOS Output Low Voltage CMOS Output High Voltage 3.0 -0.5 2.0 3.3 3.6 0.8 VCC + 0.5 0.4 V V V V V IOL = 2 mA IOH = -2 mA IOL = 100 A IOH = -100 A 1 1 1 1 1 1 2.4 0.2 VCC - 0.2 V V V53C316405A Rev. 1.2 March 1998 4 MOSEL VITELIC AC Characteristics(5,6) TA = 0 to 70 C,VCC = 3.3 V 0.3V, tT = 2 ns -50 # Symbol Parameter min. max. min. -60 V53C316405A max. Unit Note Common Parameters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period 84 30 50 8 0 8 0 8 12 10 13 40 5 1 - - 50 64 - - 10k 10k - - - - 37 25 104 40 60 10 0 10 0 10 14 12 15 50 5 1 - - - 10k 10k - - - - 45 30 - - - 50 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 Read Cycle 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 tRAC tCAC tCAA tOEA tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ tDZC tDZO tCDD tODD Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay - - - - 25 0 0 0 0 0 0 0 0 10 10 50 13 25 13 - - - - - 13 13 - - - - - - - - 30 0 0 0 0 0 0 0 0 13 13 60 15 30 15 - - - - - 15 15 - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 8 12 12 13 13 14 14 8, 9 8, 9 8,10 V53C316405A Rev. 1.2 March 1998 5 MOSEL VITELIC AC Characteristics(5,6) TA = 0 to 70 C,VCC = 3.3 V 0.3V, tT = 2 ns -50 # Symbol Parameter min. max. min. -60 V53C316405A max. Unit Note Write Cycle 31 32 33 34 35 36 37 tWCH tWP tWCS tRWL tCWL tDS tDH Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time 8 8 0 13 13 0 8 - - - - - - - 10 10 0 15 15 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15 Read-modify-Write Cycle 38 39 40 41 42 tRWC tRWD tCWD tAWD tOEH Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time 113 64 27 39 10 - - - - - 138 77 32 47 13 - - - - - ns ns ns ns ns 15 15 15 EDO Page Mode Cycle 43 44 45 46 47 48 tPC tCP tCPA tCOH tRAS tRHPC tDES EDO page mode cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in EDO mode CAS precharge to RAS Delay OE setup time prior to CAS 20 8 - 5 50 27 5 - - 27 - 200k - 25 10 - 5 60 32 5 - - 32 - 200k - ns ns ns ns ns ns ns 7 EDO Page Mode Read-modify-Write Cycle 49 50 tPRWC tCPWD EDO page mode read-write cycle time CAS precharge to WE 58 41 - - 68 49 - - ns ns CAS-before-RAS Refresh Cycle 51 52 53 54 55 tCSR tCHR tRPC tWRP tWRH CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns V53C316405A Rev. 1.2 March 1998 6 MOSEL VITELIC AC Characteristics(5,6) TA = 0 to 70 C,VCC = 3.3 V 0.3V, tT = 2 ns -50 # Symbol Parameter min. max. min. -60 V53C316405A max. Unit Note CAS-before-RAS Counter Test Cycle 56 tCPT CAS precharge time 35 - 40 - ns Test Mode 60 61 62 63 tWTS tWTH tCHRT tRAHT Write command setup time Write command hold time CAS hold time RAS hold time 10 10 30 30 - - - 10 10 30 30 - - - ns ns ns ns V53C316405A Rev. 1.2 March 1998 7 MOSEL VITELIC Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC5 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. V53C316405A 4) Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a EDO page mode cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tCAA,tCPA, tOEA . tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in readwrite cycles. V53C316405A Rev. 1.2 March 1998 8 MOSEL VITELIC Waveforms of Read Cycle t RC t RAS VIH RAS VIL t CSH t RCD VIH CAS VIL t RAD t ASR VIH Address VIL Row Column t RCH t RAH VIH WE VIL t CAA t OEA t RCS t RRH Row t ASC t CAH t RAL t ASR t RSH t CAS t CRP t RP V53C316405A VIH OE VIL t DZC t DZO t CDD t ODD I/O (Inputs) VIH VIL t CAC t OEZ Valid Data Out t RAC t OFF I/O (Outputs) VOH Hi Z VOL t CLZ Hi Z "H" or "L" WL1 V53C316405A Rev. 1.2 March 1998 9 MOSEL VITELIC Waveforms of Write Cycle (Early Write) tRC tRAS VIH RAS VIL tCSH tRCD VIH CAS VIL tRAD tASR VIH Address Row VIL tCWL tRAH VIH WE VIL tWCH tRWL VIH OE VIL tDH tWCS tWP Column tASC tCAH tRAL tASR tRSH tCAS tCRP tRP V53C316405A . Row tDS I/O (Inputs) VIH Valid Data In VIL I/O (Outputs) VOH Hi Z VOL "H" or "L" WL2 V53C316405A Rev. 1.2 March 1998 10 MOSEL VITELIC Waveforms of Write Cycle (OE Controlled Write) tRC tRAS VIH RAS VIL tCSH tRCD tRSH tCAS V53C316405A tRP tCSH VIH CAS VIL t RAD t ASR VIH Address Row VIL Column t ASC t CAH t RAL t ASR Row tCWL . t RAH VIH WE VIL tRWL tWP tOEH VIH OE VIL tDZO tDZC I/O (Inputs) VIH Valid Data VIL tCLZ tOEA VOH I/O (Outputs) Hi-Z VOL Hi-Z tOEZ tODD tDH tDS "H" or "L" WL3 V53C316405A Rev. 1.2 March 1998 11 MOSEL VITELIC Waveforms of Read-Write (Read-Modify-Write) Cycle tRWC tRAS VIH VIL RAS tRCD VIH CAS VIL tRAH tASR VIH Address VIL tRAD tAWD tCWD tRWD VIH WE VIL tCAA tRCS VIH OE VIL tDZO tDZC VIH I/O (Inputs) VIL Valid Data in tCLZ tCAC tOEZ I/O (Outputs) VOH VOL Data Out tODD tDS tDH tOEA tOEH Row Column tCWL tRWL tWP tASC tCAH tASR tCSH tRSH tCAS tCRP tRP V53C316405A Row t RAC "H" or "L" WL4 V53C316405A Rev. 1.2 March 1998 12 MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle V53C316405A tRAS VIH t RP RAS VIL tRCD tRHPC tPC tCRP VIH tRSH tCP tCAS tCAS tCRP tCAS CAS VIL tCRH tASR tRAH tASC tCAH tASC tCAH tRAL tASC tCAH VIH Address VIL Row tRAD Column 1 Column 2 Column N tRRH tRCS VIH tRCH WE VIL tCAC tCAA tOES tCPA tCAC tCAA tCPA tOFF VOH tOEA OE VOL tRAC tCAA tCAC VIH VIL tOEZ tCOH tCOH tCLZ Data Out 1 Data Out 2 Data Out N I/O (Output) WL5 "H" or "L" V53C316405A Rev. 1.2 March 1998 13 MOSEL VITELIC Waveforms of EDO Page Mode Early Write Cycle V53C316405A tRAS VIH tRP tRCD tRHPC RAS VIL tPC tCRP VIH tRSH tCP tCAS tCAS tCRP tCAS CAS VIL tCSH tASR tRAH tASC Row Addr tRAD tCWL tWCS tWCH tWP tWCS tCWL tWCH tWP tWCS tCAH tASC tCAH tASC tRAL tCAH VIH Address VIL Column 1 Column 2 Column N tRWL tCWL tWCH tWP VIH WE VIL VOH OE VOL tDS VIH tDH tDS tDH tDS tDH I/O (Input) Data In 1 VIL Data In 2 Data In N "H" or "L" WL8 V53C316405A Rev. 1.2 March 1998 14 V53C316405A Rev. 1.2 March 1998 Waveforms of EDO Page Mode Late Write and Read-Modify-Write Cycle MOSEL VITELIC tRAS VIH RAS VIL tCSH tRCD tRP tPRWC tCAS tCAS tCAS tRAL tASR tRSH tCRP VIH CAS VIL tRAD tASR tRAH tASC Row Column tRWD tCWD tCAH tCAH tASC Column tCPWD tCWD tASC Column tCWL tCPWD tCWD tCAH VIH Address VIL Row tRWL tCWL tAWD tRCS VIH tCWL WE VIL 15 tAWD tCAA tOEA tAWD tWP tOEA tWP tWP tOEA VIH OE VIL tDZC VIH tCLZ tCPA tDZC Data In tODD Data In tDZC tCPA tDZO tODD Data In tCLZ I/O (Inputs) VIL tCLZ tCAC tRAC tODD tOEZ tDS Data Out tOEH tDH tCAA tOEZ tDS Data Out tOEH tDH tCAA tOEH tCAC tDH tDS Data Out V53C316405A I/O (Outputs) WL17 VOH VOL MOSEL VITELIC Waveforms of RAS Only Refresh Cycle V53C316405A tRC tRAS VIH tRP RAS VIL tRPC VIH tCRP CAS VIL tRAH tASR tASR VIH Address VIL Row Row I/O (Outputs) VOH HI-Z VOL "H" or "L" WL9 V53C316405A Rev. 1.2 March 1998 16 MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Cycle tRC tRP VIH V53C316405A tRAS tRP RAS VIL tRPC tCP VIH tCRP tCSR tCHR tRPC CAS VIL tWRP tWRH VIH WE VIL tOEZ VIH OE VIL tCDD VIH VIL I/O (Inputs) tODD I/O (Outputs) VOH HI-Z VOL tOFF "H" or "L" WL10 V53C316405A Rev. 1.2 March 1998 17 MOSEL VITELIC Waveforms of Hidden Refresh Read Cycle tRC tRAS tRP tRC tRAS V53C316405A tRP VIH RAS VIL tRCD tRSH tCHR tCRP VIH CAS VIL tRAD tASC tRAH tASR tCAH tWRP tWRH tASR VIH Address VIL Row Column Row tRCS VIH tRRH WE VIL tCAA tOEA VIH OE VIL tDZC tDZO tCDD tODD I/O (Inputs) VIH VIL tCAC tCLZ tRAC tOEZ tOFF I/O (Outputs) VOH VOL Valid Data Out HI-Z "H" or "L" WL11 V53C316405A Rev. 1.2 March 1998 18 MOSEL VITELIC Waveforms of Hidden Refresh Early Write Cycle tRC tRP VIH V53C316405A tRC tRAS tRP tRAS RAS VIL tRCD VIH tRSH tCHR tCRP CAS VIL tRAD tRAH tASR tASC tCAH Column tWCS tWCH tWRP tWRH tASR VIH Address VIL Row Row VIH tWP WE VIL tDS VIH tDH I/O (Input) Valid Data VIL I/O (Output) VOH HI-Z VOL "H" or "L" WL12 V53C316405A Rev. 1.2 March 1998 19 MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Counter Test Cycle tRAS Read Cycle: RAS VIH VIL V53C316405A tRP tCSB CAS VIH VIL tCHR tCP tRSH tCAS tRAL tASC Address VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tCAH tASR Row tRRH tRCH Column tWRP tCAA tCAC tWRH tRCS tOEA WE OE I/O (Inputs) I/O (Outputs) tDZC tODD tDZO tCLZ tOEZ Data Out tOFF tCDD tWRP Write Cycle: WE VIH VIL tWCS tRWL tCWL tWCH tWRH OE VIH VIL tDS I/O (Inputs) I/O (Outputs) VIH VIL VIH VIL tDH Data In HI-Z V53C316405A Rev. 1.2 March 1998 20 MOSEL VITELIC Waveforms of Test Mode Entry tRC tRP VIH V53C316405A tRAS tRP RAS VIL tRPC tCP tCSR tCHRT tRPC tCRP VIH CAS VIL tASR tRAHT VIH Address VIL Row tWTS VIH tWTH WE VIL VIH OE VIL tODD I/O (Inputs) VIH HI-Z VIL tCDD tOEZ I/O (Outputs) VOH HI-Z VOL tOFF "H" or "L" WL15 V53C316405A Rev. 1.2 March 1998 21 MOSEL VITELIC Test Mode As the V53C316405A is organized internally as 4M x 4-bits, a test mode cycle using 4:1 compression can be used to improve test time. Note that in the 4M x 4 version the test time is reduced by 1/4 for a N test pattern. In a test mode "write" the data from each I/O pin is written into four 1M blocks simultaneously (all "1" s or all "0" s). In test mode "read" each I/O output is used for indicating the test mode result. If the internal four bits are equal, the I/O would indicate a "1". If V53C316405A they were not equal, the I/O would indicate a "0". The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test mode, a "CAS before RAS refresh", "RAS only refresh" or "Hidden refresh" can be used.Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. Row addresses A0 through A11 have to kept high to perform a testmode entry cycle. All other addresses are don't care. Block Diagram in Test Mode A0C,A1C A0C,A1C Normal 1 M Block 1 M Block 1 M Block 1 M Block Test A0C,A1C Vcc I/O 1 Test Normal I/O 1 Vss Vcc A0C,A1C Normal 1 M Block 1 M Block 1 M Block Normal I/O 2 Test Test I/O 2 1 M Block A0C,A1C A0C,A1C Normal Vss Vcc 1 M Block 1 M Block Normal I/O 3 Test 1 M Block 1 M Block Test I/O 3 A0C,A1C A0C,A1C Normal Vss Vcc 1 M Block 1 M Block Normal I/O 4 Test 1 M Block Test I/O 4 1 M Block Vss V53C316405A Rev. 1.2 March 1998 22 MOSEL VITELIC Package Diagrams 24/26-pin 300 mil SOJ 0.104 0.003 [2.64 0.1] 0.020 [0.5] 30 0.315 min [0.8] min 0.148 -0.020 [3.75 -0.5] 0.305 -0.009 [7.75 -0.25] 1 V53C316405A 0.008 +0.003 [0.2 +0.1] B 0.335 [0.85] Max .05 [1.27] 0.020 -0.003 [0.51 -0.1] 26 0.007 [0.18] M 24x 0.6 [15.24] 21 19 14 [0.003] 0.1 0.009 [0.25] A 0.268 0.008 [6.8 0.2] 0.340 -0.009 [8.63 -0.25] 0.009 [0.25] B 0.007 [0.18] M B 1 6 8 1 13 A Index Marking 1 0.680 -0.009 [17.27 -0.25] Units in inches [mm] Does not include plastic or metal protrusion of 0.15 max. per side 24/26-pin 300 mil TSOP-II 0.039 0.002 [1.0 0.05] 0.006 0.002 [0.150.05] 0.050 max [1.27 max] 0.3 0.005 [7.62 0.13] 0.006 +0.003 -0.004 0.15 +0.08 -0.09 5 max. 0.05 [1.27] 0.016 +0.005 -0.004 0.004 [0.1] 0.008 [0.2] M 24x 0.024 -0.008 [0.6 -0.2] 0.363 0.008 [9.22 0.2] 0.4 +0.12 -0.1 26 14 1 1 13 0.6800.005 [17.270.13] Unit in inches [mm] 1 Does not include plastic or metal protrusion of 0.15 max. per side V53C316405A Rev. 1.2 March 1998 23 MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838 V53C316405A GERMANY (CONTINENTAL EUROPE & ISRAEL ) 71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 JAPAN WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2665-4883 FAX: 852-2664-7535 IRELAND & UK BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SOUTHWESTERN SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174 CENTRAL & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 (c) Copyright 1998, MOSEL VITELIC Inc. 3/98 Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 |
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